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Samsung Electronics has revised its next-generation DRAM strategy by adding the previously project-based B1b process to its official roadmap and renaming it D0a, the company’s first sub-10-nanometer DRAM. According to ChainCatcher, the product previously referred to as D0a has now been separately classified as D0a-V, a move aimed at accelerating the introduction of advanced packaging into general-purpose DRAM.

B1b will manufacture memory cells and peripheral driver circuits on separate wafers before bonding them together using wafer-to-wafer hybrid bonding with direct copper interconnects. Current commercial DRAM is 1c, the sixth-generation 10-nanometer-class node with a line width of about 11 to 12 nanometers, while the next-generation 1d is the seventh-generation 10-nanometer-class node with a line width of about 10 to 11 nanometers and is viewed as the de facto final 10-nanometer-class product. Vertical transistor DRAM can reduce cell area from 6F² to 4F², but it faces high aspect-ratio etching and leakage challenges. Wafer-to-wafer hybrid bonding is already in mass production for CMOS image sensors and high-stack NAND.

Samsung is also evaluating B1b for its eighth-generation high-bandwidth memory, HBM5. HBM5 is expected to enter mass production around 2029 and aims to raise operating speed by more than 50% compared with HBM4E. Industry estimates say D0a DRAM based on B1b could reach commercial use in about two years, while the investment schedule for mass production may be decided as early as mid-next year.